Prof. Chris Bailey

Director of Computational Mechanics and Reliability Group

University of Greenwich

Keynote – Design Challenges for Advanced Packaging to enable a Smart and Energy Efficient World

Abstract: The Electronics Packaging Society (EPS), through its strategic plan (2019-2024), is supporting the Heterogeneous Integration Roadmap (HIR), which contains 23 chapters covering future trends and innovations in electronics packaging. Co-Design methodologies and Modelling/Simulation tools are a key part of this roadmap, which details the need for new developments in these enabling technologies. Heterogeneous Integration, through Advanced Packaging, is a critical enabling technology for future electronic systems to enable a smart world. The 2021 edition of the HIR details the technical challenges and potential solutions for advanced packaging and its applications over a 15-year timeframe. In terms of design and modelling/simulation, there is a need for new methodologies – including co-design, multi-physics, and AI –  to address these challenges. This presentation will discuss the state-of-the-art in co-design and modeling tools, the challenges that need to overcome, and potential technical solutions to these challenges for the design of future electronic systems.

Mr Chew CH

Senior Director

OnSemi

Keynote – Intelligent Power and Sensing Solutions for EV

Abstract: Vehicle electrification, autonomous driving, renewable energy and big data are enabling unprecedent changes in human life and are pushing the technology to new limits.

 

In particular for Electrical Vehicles, those major evolutions require power electronics and sensing solutions, driven by optimum technology and packaging solutions to deliver maximum product efficiency.

 

This talk will review recent progress of packaging technology and how this is to address various new challenges.

 

It will illustrate the challenges of simultaneously meeting a wide range of power density, product scalability, cost and reliability requirements.  These are made possible by the ongoing development in semiconductor research, engineering and manufacturing.

Mr Subagaran (Suba) Letchumanan

Vice President, Manufacturing and Product Engineering 

Intel Corporation (Penang) 

Keynote – Advanced Packaging  – challenges in Testability and Diagnosis

Abstract: We are moving into the era of heterogenous product integration to keep extending Moore’s Law. Industry is moving at rapid pace to build chips using various advance packaging technology by combining chiplets from different process node and technology.   Heterogenous integration have significant impact on production test, both at wafer level and at final test.  Debug and fault isolation is a key aspect when come to test. Heterogenous integration has created multiple challenges in physical debug, fault isolation and dealing with field returns. A known good die (KGD) does not mean all shipped bare die will pass at package and system.  The final package integration will need to deliver high quality and high yield packaged products.  

This keynote provides an overview of test and debug complexity and its economics brought about by heterogenous integration and what are the existing best-known method to build a manufacturable product with chiplets. We will need a high degree of innovation and collaboration among the industry to address all these challenges. 

Dr.Veer Dhandapani

Senior Director of Product Development

NXP Semiconductors

Keynote – Semiconductors for Smart Connected Devices

Abstract: The evolution of our way of life in the past few decades have been heavily influenced by waves of semiconductor innovation in processing power on the one hand, and connectivity on the other.  More than making devices “smarter”, the last decade has seen the quest transform into creating products that are smarter than any stand-alone device could be and bring AI into the mainstream.  This quest has spurred innovation and remade the definitions of even our most basic needs in society. Connectedness of everything we do – what we eat, what we wear, how we communicate, how we commute, how we work, where we need to be, all drive innovation along multiple axes.  We, as consumers of all this innovation, are the point of convergence of these tangents and how we experience it shapes the next wave of innovation.  This keynote will focus on this next wave and how artificial intelligence, connected devices large and small (from cars to wrist watches) are spurring innovations in product designs and packaging technology.  We will discuss how technology innovation, specifically packaging, will enable the Sense, Think, Connect and Act product paradigms and make possible a whole new world of use cases, in the home, in the car, and in industrial and retail environments.

Mr. Laurent Herard

Group VP – Head of Back End Manufacturing and Technology R&D

STMicroelectronics

Keynote – Packaging Innovation – A key enabler for a smart world

Abstract: Electronics industry has been evolving from a “hardware centric” application to a “user centric” application, leading the electronics system design from a “component assembly” to a “system integration” approach. New interconnection design and solutions are needed.

 

Wafer level packaging, fan in and fan out WLCSP mainly, is being widely adopted to build highly miniaturized IoT mobile electronics hardware. Fan in WLCSP is becoming a dominant packaging solution for low to medium pin count IC in wearable and mobile electronics while fan out is quickly gaining popularity for application processor in personal electronics and 77 GHz radar chip for automotive.

 

System in Package (SiP) is making the buzz in our industry. The concept of Multi Chip Module (MCM) or Multichip Package (MCP) has been brought to real products in the early 2000’s. Up to recently, the silicon nodes roadmap and the mixed technology progresses have made System On Chip (SOC) the winner for system design.

 

IoT is everywhere. With about 45 billion connected objects at the end of 2021, our society is on the way to a fast digital transformation. The performance requirement for data server and Artificial Intelligence (AI) drives the adoption in mass production of the most advanced interconnect technologies such TSV for memory cube, 2.5D interposer with ultra-fine pitch flip chipped IC and mixed CMOS nodes.

 

Automotive is another “hot” topic for today packaging industry. Semiconductor solution is the key to achieve a safer, greener and more connected driving experience. Processing power embarked in latest generation cars keeps increasing and advanced packaging solutions, designed for high end consumer computing, are being tuned and qualified for automotive. This is typically the case of fine pitch flip chip or 2.5D used to package ADAS processors.

 

Packaging industry is enjoying a formidable innovation momentum. Electronics for a smart world is leading to a convergence of packaging R&D among applications. A laser sensor package for mobile phone is requiring development of high thermal conductivity die attach material, designed for power IC, while latest generation ADAS chip will require a fine pitch copper pillar flip chip package, traditionally used for consumer computing processor. This convergence is the opportunity for more cross-fertilization to boost packaging R&D and a lot of “technical fun” for the packaging engineers.

Bernhard Knot

Head of Backend Innovation Infineon

Keynote – Success Factors for innovative and reliable Package Solutions

Abstract: Global Megatrends like demographic & social change, climate change & resource scarcity, urbanization as well as digital transformation underline the importance of electronics. These Megatrends are shaping the automotive market which result in a significant increase of semiconductor content per car. In addition system in package integration is becoming more and more important in assembly and package industry. We observe integration of more functionality into packages of smaller volume in nearly all kind of electronic applications. As dimensions get smaller and smaller we face changing requirements for package materials. A sustainable and deep knowhow on materials and interfaces will be the key for successful future developments. Understanding and control of material interaction (chemistry, thermo-mechanical) and thermal management are key enabling factors for a quick market introduction of new products. In the last 10 years all package materials changed and this trend will proceed. For development of a new package and package technology understanding and modeling the coherence for Chip – Package- Board Materials will make the difference for reliable system integration.

 

This presentation will introduce System integration solutions with respect to concepts, materials and processes and will show success factors for innovative and reliable Package Solutions enabling fast commercialization.

E. Jan Vardaman

President and Founder of

TechSearch International, Inc

Keynote – Electronics Industry Growth Markets: Package Choices, Challenges, and Trend

Abstract: The electronics industry continues to see growth in datacenter, 5G infrastructure and automotive electronics. The move to electric vehicles (EV) is driving adoption of wide band gap materials and new packages. Power devices are increasingly important, and new form factors including embedded structure are being adopted for these applications. Many packages are leadframe-based packages. QFN remains the workhorse of the industry. Demand for Cu clip packages is increasing. What are the package choices for these application areas and how are the options changing? What infrastructure and material challenges does the industry face? This presentation discusses these growth drivers and packaging trends in each area.