IEMT2022 Short Course

Welcome!

 

The 2022 IEMT Conference Short Courses will be held on 19th October 2022 (Wednesday). With speakers from a broad diversity of interest and experience, the goal is to offer beneficial electronic packaging courses to enhance our members’ technical knowledge. Five courses have been selected covering diverse areas of electronic packaging technology topics and all courses will be conducted in-person. You can now Register Here for the Short Courses.

 

2022 IEMT Committee

Session 1: Half-Day (19th October 2022, 8:30am to 12:30pm)

Prof Tan Chuan Seng
University Professor
Nanyang University, Singapore

Short Course – Advanced Packaging and Integration – Drivers, Technology Platforms, Challenges and Applications

Abstract: The main objective of this course is to allow the attendees to appreciate the roles and value-adds of advanced packaging in IC manufacturing. In preparation for future trends and needs, the bulk of this course will focus on emerging topics in 3D packaging and the role of through silicon via (TSV). Silicon interposer based 2.5D packaging is also discussed, as well as fan-out packaging and monolithic 3D. Upon successful completion of this course, attendees are expected to acquire knowledge and understanding about related enabling technology in emerging 2.5D/3D packaging. The following topics are covered: (1) Progression to 3D packaging and integration, (2) Enablers and Platforms, (3) Process Integrations and Schemes, (4) Current and Future Applications, (5) Fan-out, (6) 2.5D Interposer, (7) Monolithic 3D IC, (8) Reliability and Manufacturing Challenges, and (9) Opportunities and Outlooks.

Biography: Chuan Seng Tan is a Professor of Electronic Engineering at the School of Electrical and Electronic Engineering at Nanyang Technological University, Singapore. He received his PhD from MIT in 2006. Currently, he is working on process technology of three-dimensional integrated circuits (3-D ICs), as well as engineered substrate (Si/Ge/Sn) for group-IV photonics. He has numerous publications (journal and conference) and IPs on 3-D technology and engineered substrates. Nine of his inventions have since been licensed to a spin-off company. He co-edited/co-authored five books on 3D packaging technology.

 

He is a Fellow of IEEE (Class of 2022) and a recipient of the Exceptional Technical Achievement Award from the IEEE Electronics Packaging Society (EPS) in 2019. Beginning June 2019, he is a Distinguished Lecturer with IEEE-EPS. He is a Fellow of the International Microelectronics Assembly and Packaging Society (IMAPS) since 2019 and a recipient of the William D. Ashman – John A. Wagnon Technical Achievement Award in 2020.

 

He was the Chair of the Interconnections Sub-Committee for ECTC’2021. He was the General Chair of the 2020 IEEE Electronics Packaging Technology Conference (EPTC-Virtual). In addition, he is an Associate Editor for the IEEE Transactions on Components, Packaging and Manufacturing Technology and was recognized with the Best Associate Editor Award in 2021. He serves as an elected Member-at-Large to the IEEE EPS Board of Governors from 2022-2024.

Session 1: Half-Day (19th October 2022, 1:30am to 5:30pm)

Prof Swami

Professor

Georgia Institute of Technology, USA

Short Course – Power Electronics, Power Delivery, Thermal Management, and Heterogeneous Integration: Their Interplay that will define the Future of Semiconductor Systems

Abstract: The semiconductor industry is headed towards heterogeneous integration in 2.5D or 3D form being driven by the high cost of monolithic integration, extended time to market using advanced process nodes on large designs, and heterogeneity of systems. This is great news for packaging.    

As systems scale, heterogeneous integration approaches are becoming increasingly useful for managing power. However, unique challenges are emerging that requires innovative approaches for integrating power electronics into the solution to maximize efficiencies in power delivery. Since power delivery and thermal management are interlocked, new mechanisms for heat removal are becoming necessary.

This short course will cover the fundamentals of power electronics and power delivery in the context of computing, describe what has been achieved so far, discuss the advances emerging in heterogeneous integration, the challenges that need to be addressed moving forward as AI applications emerge, as well as new technologies such as glass interposers and fan-out wafer level packaging that can play a significant role in meeting the challenges of the future.

Biography: Madhavan Swaminathan is the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE), Professor in ECE with a joint appointment in the School of Materials Science and Engineering (MSE), and Director of the 3D Systems Packaging Research Center (PRC), Georgia Tech (GT) (http://www.prc.gatech.edu). He also serves as the Site Director for the NSF Center for Advanced Electronics through Machine Learning (CAEML: https://publish.illinois.edu/advancedelectronics/) and Theme Leader for Heterogeneous Integration, at the SRC JUMP ASCENT Center (https://ascent.nd.edu/). Prior to joining GT, he was with IBM working on packaging for supercomputers.

 

He is the author of 550+ refereed technical publications and holds 31 patents. He is the primary author and co-editor of 3 books and 5 book chapters, founder and co-founder of two start-up companies, and founder of the IEEE Conference on Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the IEEE Electronics Packaging Society (EPS). He is an IEEE Fellow and has served as the Distinguished Lecturer for the IEEE Electromagnetic Compatibility (EMC) society.

 

He received his MS and PhD degrees in Electrical Engineering from Syracuse University in 1989 and 1991, respectively.

Session 2: Full-Day (19th October 2022, 8:30am to 5:30pm)

Mr Azham

Senior Staff Engineer

NXP Semiconductors, Malaysia

Short Course – Flip Chip Packaging – Key Processes Attributes, Challenges and Resolution

Abstract: The main objective of this course is to provide an overview of critical attributes in flip chip packaging for a sustainable manufacturing processes. Flip chip packaging is considered the oldest in advanced packaging family which was commercially introduced by IBM in the 1960s. The advantages of using flip chip interconnect makes the packaging is still valid until today. Reduced signal/power/ground inductance, higher signal density, reduced package footprint, die shrink enabler, and better thermal performance are among the advantages. The attendees will be introduced with critical flip chip processes, common issues in each process, current solutions, and some insight of advanced approach to meet today’s package structure challenges.

Biography: Azham Mohd Sukemi received the Bsc in Mechanical Engineering from the Bradley University, Peoria Illinois USA in 1992 and Msc in Semiconductor Packaging Technology from the National University of Malaysia, Selangor Malaysia in 1997. He had been with the semiconductor packaging industry for 30 years, working from traditional Quad Flat Package to the recent advanced flip-chip packages. He joined Motorola in 1992 as a process engineer and currently as Sr Principal Engineer in Package Innovation for NXP Malaysia Sdn. Bhd.

JaeYun Kim

Staff Engineer

NXP Semiconductors, South Korea

Short Course – Flip Chip Packaging – Key Processes Attributes, Challenges and Resolution

Abstract: The main objective of this course is to provide an overview of critical attributes in flip chip packaging for a sustainable manufacturing processes. Flip chip packaging is considered the oldest in advanced packaging family which was commercially introduced by IBM in the 1960s. The advantages of using flip chip interconnect makes the packaging is still valid until today. Reduced signal/power/ground inductance, higher signal density, reduced package footprint, die shrink enabler, and better thermal performance are among the advantages. The attendees will be introduced with critical flip chip processes, common issues in each process, current solutions, and some insight of advanced approach to meet today’s package structure challenges.

Biography: JaeYun Kim received the Bachelor’s degree in Material Engineering from the SungKyunKwan University, Republic of Korea in 2000. He had been with semiconductor packaging industry for 22 years, working from material, process development for W/B and F/C to development of the recent advanced flip-chip packages. He had worked in Amkor technology from 2000 as a RND engineer for 20 years and then he joined as staff Engineer in Package Innovation for NXP Korea in 2020.

Session 3: Full-Day (19th October 2022, 8:30am to 5:30pm)

Prof Fan Xuejun

University Professor

Lamar University, USA

Short Course – Reliability Mechanics Modeling and Simulation in Electronic Packaging – Thermo-Mechanics, Moisture, Dynamics and Electromigration

Abstract: This course aims to present a comprehensive coverage of multi-physics modeling and simulation for mechanics related reliability issues under various loading conditions. In addition to the introduction of fundamentals, the course contents are arranged in four modules. Module 1 covers modeling under thermal loading, such as first level failure (TSV/bump/dielectric), warpage, and temperature cycling. Module 2 deals with the modeling under mechanical loading, such as drop impact. Module 3 will cover modeling under humidity/moisture loading for moisture related problems, such as failures in soldering reflow as well as under HAST. Module 4 will focus on electromigration modeling that involves with electrical, thermal, mechanical and diffusion modeling. Theoretical foundation, modeling implementation, and the best practices for simulation will be covered. Emerging trend and future perspective in reliability mechanics and modeling will be discussed.

Biography: Xuejun Fan is a Regents’ Professor of Texas State University System, a Mary Ann and Lawrence E. Faust endowed chair professor in the Department of Mechanical Engineering at Lamar University, Beaumont, Texas. He received his Ph.D. degree in solid mechanics from Tsinghua University, Beijing, China in 1989. His interests and research lie in the area of modeling, characterization and reliability in heterogeneous integration in microelectronics. Dr. Fan had extensive experience in industry, such as with Intel Cooperation, Philips Research, and the Institute of Microelectronics (IME), Singapore. Dr. Fan received the Outstanding Sustained Technical Contribution Award in 2017, and the Exceptional Technical Achievement Award in 2011 from IEEE Electronic Packaging Society (EPS). He is an Associate Editor of IEEE Transactions on Components, Packaging and Manufacturing Technology and Microelectronics Reliability. Dr. Fan is an IEEE Fellow and a Distinguished Lecturer. He serves as chair, co-chairs, and committee members of various conferences such as ECTC, EPTC, ESTC, EuroSimE, ICEPT, ESREF, and EMPT. He has published more than 300 papers, including 4 books, over 100 journal papers, many book chapters, and numerous conference papers. Dr. Fan currently serves as a member-at-large of the IEEE Electronic Packaging Society (EPS) Board of Governors, and a co-chair of Modeling and Simulation in Heterogeneous Integration Roadmap (HIR).

 

Session 4: Full-Day (19th October 2022, 8:30am to 5:30pm)

John H Lau

Professor

Unimicron Technology Corporation, Taiwan

Short Course – Fan-out Packaging and Chiplet Heterogeneous Integration

Abstract: Fan-out wafer/panel-level packaging has been getting lots of tractions since TSMC used their integrated fan-out to package the application processor chipset for the iPhone 7. In this lecture, the following topics will be presented and discussed. Emphasis is placed on the fundamentals and latest developments of these areas in the past few years. Their future trends will also be explored. Chiplet is a chip design method and heterogeneous integration (HI) is a chip packaging method. HI uses packaging technology to integrate dissimilar chips, photonic devices, and/or components (either side-by-side, stacked, or both) with different sizes and functions, and from different fabless design houses, foundries, wafer sizes, and feature sizes into a system or subsystem on a common package substrate. These chips can be any kind of devices and don’t have to be chiplets. On the other hand, for chiplets, they have to use the heterogeneous integration to package them. For the next few years, we will see more implementations of a higher level of chiplet designs and HI packaging, whether it is for time-to-market, performance, form factor, power consumption or cost. In this lecture, the introduction, recent advances, and trends in chiplet design and HI packaging will be presented.

Biography: John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging and SMT assembly, has published more than 510 peer-reviewed papers, 40 issued and pending US patents, and 22 textbooks on, e.g., Reliability of RoHS compliant 2D & 3D IC Interconnects (McGraw-Hill, 2011), Through-Silicon Via (TSV) for 3D Integration (McGraw-Hill, 2013), 3D IC Integration and Packaging (McGraw-Hill, 2016), and Assembly and Reliability of Lead-Free Solder Joints (Springer, 2020). John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.