IEMT2022 Short Course

Welcome!

 

The 2022 IEMT Conference Short Courses will be held on 19th October 2022 (Wednesday). With speakers from a broad diversity of interest and experience, the goal is to offer beneficial electronic packaging courses to enhance our members’ technical knowledge. Five courses have been selected covering diverse areas of electronic packaging technology topics and all courses will be conducted in-person. You can now Register Here for the Short Courses.

 

2022 IEMT Committee

Session 1A: Half-Day (19th October 2022, 8:30am to 12:30pm) at Gallery 1 (Level2)

Prof Tan Chuan Seng
Professor
Nanyang Technological University, Singapore

Short Course – Advanced Packaging and Integration – Drivers, Technology Platforms, Challenges and Applications

Abstract: The main objective of this course is to allow the attendees to appreciate the roles and value-adds of advanced packaging in IC manufacturing. In preparation for future trends and needs, the bulk of this course will focus on emerging topics in 3D packaging and the role of through silicon via (TSV). Silicon interposer based 2.5D packaging is also discussed, as well as fan-out packaging and monolithic 3D. Upon successful completion of this course, attendees are expected to acquire knowledge and understanding about related enabling technology in emerging 2.5D/3D packaging. The following topics are covered: (1) Progression to 3D packaging and integration, (2) Enablers and Platforms, (3) Process Integrations and Schemes, (4) Current and Future Applications, (5) Fan-out, (6) 2.5D Interposer, (7) Monolithic 3D IC, (8) Reliability and Manufacturing Challenges, and (9) Opportunities and Outlooks.

Biography: Chuan Seng Tan is a Professor of Electronic Engineering at the School of Electrical and Electronic Engineering at Nanyang Technological University, Singapore. He received his PhD from MIT in 2006. Currently, he is working on process technology of three-dimensional integrated circuits (3-D ICs), as well as engineered substrate (Si/Ge/Sn) for group-IV photonics. He has numerous publications (journal and conference) and IPs on 3-D technology and engineered substrates. Nine of his inventions have since been licensed to a spin-off company. He co-edited/co-authored five books on 3D packaging technology. He is a Fellow of IEEE (Class of 2022) and a recipient of the Exceptional Technical Achievement Award from the IEEE Electronics Packaging Society (EPS) in 2019. Beginning June 2019, he is a Distinguished Lecturer with IEEE-EPS. He is a Fellow of the International Microelectronics Assembly and Packaging Society (IMAPS) since 2019 and a recipient of the William D. Ashman – John A. Wagnon Technical Achievement Award in 2020. He was the Chair of the Interconnections Sub-Committee for ECTC’2021. He was the General Chair of the 2020 IEEE Electronics Packaging Technology Conference (EPTC-Virtual). In addition, he is an Associate Editor for the IEEE Transactions on Components, Packaging and Manufacturing Technology and was recognized with the Best Associate Editor Award in 2021. He serves as an elected Member-at-Large to the IEEE EPS Board of Governors from 2022-2024.

Session 1B: Half-Day (19th October 2022, 1:30pm to 5:30pm) at Gallery 1 (Level 2)

Prof Swami

Professor

Georgia Institute of Technology, USA

Short Course – Power Electronics, Power Delivery, Thermal Management, and Heterogeneous Integration: Their Interplay that will define the Future of Semiconductor Systems

Abstract: The semiconductor industry is headed towards heterogeneous integration in 2.5D or 3D form being driven by the high cost of monolithic integration, extended time to market using advanced process nodes on large designs, and heterogeneity of systems. This is great news for packaging.    

As systems scale, heterogeneous integration approaches are becoming increasingly useful for managing power. However, unique challenges are emerging that requires innovative approaches for integrating power electronics into the solution to maximize efficiencies in power delivery. Since power delivery and thermal management are interlocked, new mechanisms for heat removal are becoming necessary.

This short course will cover the fundamentals of power electronics and power delivery in the context of computing, describe what has been achieved so far, discuss the advances emerging in heterogeneous integration, the challenges that need to be addressed moving forward as AI applications emerge, as well as new technologies such as glass interposers and fan-out wafer level packaging that can play a significant role in meeting the challenges of the future.

Biography: Madhavan Swaminathan is the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE), Professor in ECE with a joint appointment in the School of Materials Science and Engineering (MSE), and Director of the 3D Systems Packaging Research Center (PRC), Georgia Tech (GT) (http://www.prc.gatech.edu). He also serves as the Site Director for the NSF Center for Advanced Electronics through Machine Learning (CAEML: https://publish.illinois.edu/advancedelectronics/) and Theme Leader for Heterogeneous Integration, at the SRC JUMP ASCENT Center (https://ascent.nd.edu/). Prior to joining GT, he was with IBM working on packaging for supercomputers. He is the author of 550+ refereed technical publications and holds 31 patents. He is the primary author and co-editor of 3 books and 5 book chapters, founder and co-founder of two start-up companies, and founder of the IEEE Conference on Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the IEEE Electronics Packaging Society (EPS). He is an IEEE Fellow and has served as the Distinguished Lecturer for the IEEE Electromagnetic Compatibility (EMC) society. He received his MS and PhD degrees in Electrical Engineering from Syracuse University in 1989 and 1991, respectively.

Session 2: Full-Day (19th October 2022, 8:30am to 5:30pm) at Gallery 4 & 5 (Level 2)

Mr Azham

Senior Staff Engineer

NXP Semiconductors, Malaysia

Short Course – Flip Chip Packaging – Key Processes Attributes, Challenges and Resolution

Abstract: The main objective of this course is to provide an overview of critical attributes in flip chip packaging for a sustainable manufacturing processes. Flip chip packaging is considered the oldest in advanced packaging family which was commercially introduced by IBM in the 1960s. The advantages of using flip chip interconnect makes the packaging is still valid until today. Reduced signal/power/ground inductance, higher signal density, reduced package footprint, die shrink enabler, and better thermal performance are among the advantages. The attendees will be introduced with critical flip chip processes, common issues in each process, current solutions, and some insight of advanced approach to meet today’s package structure challenges.

Biography: Azham Mohd Sukemi received the Bsc in Mechanical Engineering from the Bradley University, Peoria Illinois USA in 1992 and Msc in Semiconductor Packaging Technology from the National University of Malaysia, Selangor Malaysia in 1997. He had been with the semiconductor packaging industry for 30 years, working from traditional Quad Flat Package to the recent advanced flip-chip packages. He joined Motorola in 1992 as a process engineer and currently as Sr Principal Engineer in Package Innovation for NXP Malaysia Sdn. Bhd.

JaeYun Kim

Staff Engineer

NXP Semiconductors, South Korea

Short Course – Flip Chip Packaging – Key Processes Attributes, Challenges and Resolution

Abstract: The main objective of this course is to provide an overview of critical attributes in flip chip packaging for a sustainable manufacturing processes. Flip chip packaging is considered the oldest in advanced packaging family which was commercially introduced by IBM in the 1960s. The advantages of using flip chip interconnect makes the packaging is still valid until today. Reduced signal/power/ground inductance, higher signal density, reduced package footprint, die shrink enabler, and better thermal performance are among the advantages. The attendees will be introduced with critical flip chip processes, common issues in each process, current solutions, and some insight of advanced approach to meet today’s package structure challenges.

Biography: JaeYun Kim received the Bachelor’s degree in Material Engineering from the SungKyunKwan University, Republic of Korea in 2000. He had been with semiconductor packaging industry for 22 years, working from material, process development for W/B and F/C to development of the recent advanced flip-chip packages. He had worked in Amkor technology from 2000 as a RND engineer for 20 years and then he joined as staff Engineer in Package Innovation for NXP Korea in 2020.

Session 3A: Half-Day (19th October 2022, 8:30am to 12:30pm) at Gallery 6 (Level 2)

Prof Fan Xuejun

University Professor

Lamar University, USA

Short Course – Reliability Mechanics Modeling and Simulation in Electronic Packaging – Thermo-Mechanics, Moisture, Dynamics and Electromigration

Abstract: This course aims to present a comprehensive coverage of multi-physics modeling and simulation for mechanics related reliability issues under various loading conditions. In addition to the introduction of fundamentals, the course contents are arranged in four modules. Module 1 covers modeling under thermal loading, such as first level failure (TSV/bump/dielectric), warpage, and temperature cycling. Module 2 deals with the modeling under mechanical loading, such as drop impact. Module 3 will cover modeling under humidity/moisture loading for moisture related problems, such as failures in soldering reflow as well as under HAST. Module 4 will focus on electromigration modeling that involves with electrical, thermal, mechanical and diffusion modeling. Theoretical foundation, modeling implementation, and the best practices for simulation will be covered. Emerging trend and future perspective in reliability mechanics and modeling will be discussed.

Biography: Xuejun Fan is a Regents’ Professor of Texas State University System, a Mary Ann and Lawrence E. Faust endowed chair professor in the Department of Mechanical Engineering at Lamar University, Beaumont, Texas. He received his Ph.D. degree in solid mechanics from Tsinghua University, Beijing, China in 1989. His interests and research lie in the area of modeling, characterization and reliability in heterogeneous integration in microelectronics. Dr. Fan had extensive experience in industry, such as with Intel Cooperation, Philips Research, and the Institute of Microelectronics (IME), Singapore. Dr. Fan received the Outstanding Sustained Technical Contribution Award in 2017, and the Exceptional Technical Achievement Award in 2011 from IEEE Electronic Packaging Society (EPS). He is an Associate Editor of IEEE Transactions on Components, Packaging and Manufacturing Technology and Microelectronics Reliability. Dr. Fan is an IEEE Fellow and a Distinguished Lecturer. He serves as chair, co-chairs, and committee members of various conferences such as ECTC, EPTC, ESTC, EuroSimE, ICEPT, ESREF, and EMPT. He has published more than 300 papers, including 4 books, over 100 journal papers, many book chapters, and numerous conference papers. Dr. Fan currently serves as a member-at-large of the IEEE Electronic Packaging Society (EPS) Board of Governors, and a co-chair of Modeling and Simulation in Heterogeneous Integration Roadmap (HIR).

Session 3B: Half-Day (19th October 2022, 1:30pm to 5:30pm) at Gallery 6 (Level 2)

Prof. Andrew Tay

EPS Director of Region 10 Programs

National University of Singapore

Short Course – Analysis of Delamination in Microelectronics Packages

Abstract: A microelectronic package is composed of different materials. When it undergoes a temperature increase during solder reflow, the different constituent materials expand at different rates giving rise to thermal stresses within the package. When such stresses become excessive, delaminations or fracture will occur. It has been found that it is impossible to predict failure using a maximum stress failure criterion due to stress singularities at the corners within the package. On the other hand, a fracture mechanics approach has been found to be successful in predicting thermomechanical failure in microelectronic packages. For plastic-encapsulated packages, an additional stress called hygrostress is developed due to moisture absorption in the plastic encapsulant

The objective of this short course is to provide an overview of the analysis of delamination in plastic microelectronic packages using the fracture mechanics approach. The mechanism of popcorn cracking failure will be described and analysed. Simulation of heat transfer and moisture diffusion processes occurring during package qualification will be described. An introduction to the fundamentals of interfacial fracture mechanics will be given together with a brief description of some numerical methods of calculating fracture mechanics parameters. Experiments which verify the methodology for predicting delamination in packages will then be described followed by some interesting case studies. Some techniques for detecting delaminations and voids in packages, including 3D packages will also be described

Biography: Prof Andrew Tay is currently a Visiting Scientist at the Singapore Hybrid-Integrated Next-Generation ì-Electronics Centre (SHINE), National University of Singapore. He was a Professor of Mechanical Engineering at the National University of Singapore. He obtained his B.E. (Hons I and University Medal) and PhD in Mechanical Engineering from the University of New South Wales, Australia. His research interests include electronics packaging (thermo-mechanical failures, delamination, effects of moisture, solder joint reliability); thermal management of electronic systems and EV batteries, infrared and thermo-reflectance thermography, solar photovoltaics reliability and fracture mechanics. He is currently the Director of Region 10 Programs and a member of the Board of Governors of the IEEE Electronics Packaging Society (EPS) and a member of the Executive Committee of the IEEE Singapore RS/EPS/EDS Chapter. He was the inaugural General Chair of the 1st Electronics Packaging Technology Conference (EPTC) in 1997 and currently the Chairman of the EPTC Board. He was awarded the 2019 IEEE EPS David Feldman Outstanding Contribution Award, the 2012 IEEE CPMT Exceptional Technical Achievement Award, and the 2012 IEEE CPMT Regional Contributions Award. For his outstanding contributions in the application of engineering mechanics to electronics and/or photonics packaging, he was awarded the ASME EPPD Engineering Mechanics Award in 2004. He was also awarded an IEEE Third Millennium Medal in 2000. He is a Fellow of ASME and a Senior Member of IEEE.

Session 4A: Half-Day (19th October 2022, 8:30am to 12:30pm) at Gallery 2 & 3 (Level 2)

John H Lau

Professor

Unimicron Technology Corporation, Taiwan

Short Course – Fan-out Packaging and Chiplet Heterogeneous Integration

Abstract: This lecture will cover the followings. (1) Formation of FOWLP: (a) Chip-First (Die Face-Down), (b) Chip-First (Die Face-Up), and (c) Chip-Last (or RDL-First). (2) Redistribution Layers (RDLs): (a) Polymer and ECD Cu + Etching, (b) PECVD and Cu Damascene + CMP, (c) Hybrid RDLs, and (d) Laser drill + LDI + PCB Cu-plating + Etching. (3) Formation of FOPLP: (a) Chip-First (Die Face-Down), (b) Chip-First (Die Face-Up), and (c) Chip-Last (or RDL-First). (4) TSMC InFO: (a) InFO-PoP, and (b) InFO_AiP Driven by 5G mmWave. (5) Samsung PLP: (a) PoP for Smart Watches and (b) SiP SbS for Smartphones. (6) Warpages: (a) Warpage Types and (b) Allowable of Warpages. (7) Reliability of FOWLP and FOPLP: (a) Thermal-Cycling Test, (b) Thermal-Cycling Simulations, (c) Drop Test, and (d) Drop Simulations. (8) Examples: (a) Chip-First Panel-Level Fan-Out Packaging of Mini-LED for RGB-Display, (b) Chip-Last Panel-Level Fan-Out Packaging of Application Processor Chipset, (c) 2.3D IC Integration with Chip-First Fan-Out RDL-Interposers, and (d) 2.3D IC Integration with Chip-Last Fan-Out RDL-Interposers. (9) Chiplet Design and HI Packaging vs. System-on-Chip (SoC). (10) Advantages and Disadvantages of Chiplet Design and HI Packaging. (11) Examples: (a) Xilinx Chiplet Design and HI Packaging (Virtex), (b) AMD Chiplet Design and HI Packaging (EPYZ and RYZEN), (c) Intel Chiplet Design and HI Packaging (FOVEROS, FOVEROS Direct, and Ponte Vecchio), and (d) TSMC Chiplet Design and HI Packaging (SoIC + CoWoS and SoIC + InFO PoP). (12) Chiplets Lateral Interconnects (Bridges): (a) Intel’s EMIB, (b) IBM’s DBHi, (c) Applied Materials’ Bridge Embedded in Fan-Out EMC, (d) SPIL’s FO-EB, (e) TSMC’s LSI, (f) ASE’s sFOCoS, (g) IME’s EFI, (h) Amkor’s S-Connect Fan-Out Interposer, and (i) UCIe. (13) Chiplet Design and HI Packaging on Organic Substrates (SiP): many examples. (14) Chiplet Design and HI Packaging on Silicon Substrates (TSV-Interposers): many examples: (a) Leti, (b) IME, (c) HKUST, (d) ITRI, (e) Xilinx/TSMC, (f) Altera/TSMC, (g) NVidia/TSMC, (h) AMD/UMC, (i) AMD’s Active Interposer, (j) Intel’s FOVEROS Direct and Ponte Vecchio, (k) TSMC’s SoIC, and (l) Samsung’s X-Cube and H-Cube. (15) Chiplet Design and HI Packaging on Fan-Out RDL Substrate for High Performance Applications: many examples: (a) STATSChipPac’s FOFC-eWLB, (b) ASE’s FOCoS (Chip-First), (c) MediaTek’s FO-RDLs, (d) TSMC’s InFO_oS and InFO_MS, (e) Samsung’s Si-Less RDL Interposer, (f) TSMC’s RDL-Interposer, (g) ASE’s FOCoS (Chip-Last), (h) Shinko’s Organic RDL-Interposer, and (i) Unimicron’s Hybrid Substrate. (16) Assembly Technologies for Chiplet Design and HI Packaging: (a) SMT, (b) Solder Bumped Flip Chip, (c) CoW, (d) WoW, (e) TCB, and (f) Bumpless Cu-Cu Hybrid Bonding.

Biography: John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging and SMT assembly, has published more than 515 peer-reviewed papers, 40 issued and pending US patents, and 22 textbooks on, e.g., Reliability of RoHS compliant 2D & 3D IC Interconnects (McGraw-Hill, 2011), Through-Silicon Via (TSV) for 3D Integration (McGraw-Hill, 2013), 3D IC Integration and Packaging (McGraw-Hill, 2016), Assembly and Reliability of Lead-Free Solder Joints (Springer, 2020), and Semiconductor Advanced Packaging (Springer, 2021). John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.

Session 4B: Half-Day (19th October 2022, 1:30pm to 5:30pm) at Gallery 2 & 3 (Level 2)

Prof. Kuan Yew Cheong

Professor

UNIVERSITI SAINS MALAYSIA

Short Course – Advanced Packaging Challenges and Investigation Strategies

Abstract: Failure is unavoidable in all engineering products, which includes advanced packages for Internet of Things (IoTs). In order to minimize failure and to improve quality, robustness, and reliability of a product, investigation of failure is an important and yet complex activity that require integration of diverse knowledge of science and engineering. Systematic, effective, and data driven approaches must be adopted during the process of investigation, particularly in the era of IoTs with high expectation. In this short course, basic strategy of analysing failures of electronic materials used in advanced packaging will be elaborated. Importance of equipping with fundamental and technological knowledge to establish failure mechanisms, nail down possible root causes, and propose feasible solution of issues will be presented. Essential components of knowledge based on octagonal relationship of electronic materials to resolve issues of engineering products during failure investigation will be explained.

Biography: As a passionate researcher, educator, trainer, consultant, and Professional Engineer of material science and engineering for more than twenty-five years, Kuan Yew CHEONG is a full Professor at the School of Materials and Mineral Resources Engineering, Universiti Sains Malaysia (USM), Malaysia. Prof. Cheong served as a Commissioned Senior Scientist at Korea Electrotechnology Research Institute (2004, 2006), Adjunct Associate Professor at Multimedia University, Malaysia (2012), Visiting Lecturer at Universiti Malaysia Perlis, Malaysia (2012), Visiting Professor at National Taiwan University (2018), MIMOS Semiconductor Sdn Bhd (2018), Technical Advisor for NTG Innovation Pte. Ltd., Singapore (January – December 2019), affiliated to Innovation Centre for Clean Water and Sustainable Energy (WISE), National Tsing Hua University, Taiwan (November 2018 to October 2021), and Editor of “Materials Science in Semiconductor Processing”, Elsevier (2015 – June 2021). Currently, he is an External Examiner for Wawasan Open University (Malaysia), INTI International College Penang (Malaysia), Technical Consultant of failure analysis for MIMOS Semiconductor Sdn Bhd (Malaysia), Visiting Professor at the State Key Laboratory of Crystal Materials, Institute of Novel Semiconductor Materials, Shandong University, China (Jan 2022 – Dec 2023), Editor-in-Chief of “Materials Science in Semiconductor Processing”, Elsevier (since July 2021), and Editor-in-Chief of “Journal of Minerals and Materials Engineering”, USM (since March 2022). He has published more than 245 high impact-factor journals, 6 reputable book chapters, 4 edited books, and 1 granted Malaysian Patent (MY-153033-A), which are aligned to his research direction of solving environmental and energy related issues through the development of advanced dielectrics for wide bandgap semiconductor devices and of natural organic materials for sustainable electronic devices. As a registered Professional Engineer (Board of Engineers, Malaysia), a “Top Research Scientists Malaysia (TRSM)” (Academy of Sciences Malaysia), and an Accredited and Certified Professional Trainer (HRD Corp., Malaysia), Prof. Cheong has delivered more than 350 technical training courses to various local and multinational industries and resolved many industrial cases related to processing and reliability of electronic materials both wafer and package levels. Currently, Prof. Cheong is a Fellow of The Institution of Engineers Malaysia (IEM), Senior Member of Institute of Electrical, Electronic Engineers (IEEE), a Principal Interviewer for Professional Interview of IEM, Senior Evaluation Panel of Engineering Program Accreditation under Engineering Accreditation Council, Malaysia, and Founding Chairman of Material Engineering Technical Division under IEM.